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       1                 :             : /* x86 linux perf_events register handling, pieces common to x86-64 and i386.
       2                 :             :    Copyright (C) 2025 Red Hat, Inc.
       3                 :             :    This file is part of elfutils.
       4                 :             : 
       5                 :             :    This file is free software; you can redistribute it and/or modify
       6                 :             :    it under the terms of either
       7                 :             : 
       8                 :             :      * the GNU Lesser General Public License as published by the Free
       9                 :             :        Software Foundation; either version 3 of the License, or (at
      10                 :             :        your option) any later version
      11                 :             : 
      12                 :             :    or
      13                 :             : 
      14                 :             :      * the GNU General Public License as published by the Free
      15                 :             :        Software Foundation; either version 2 of the License, or (at
      16                 :             :        your option) any later version
      17                 :             : 
      18                 :             :    or both in parallel, as here.
      19                 :             : 
      20                 :             :    elfutils is distributed in the hope that it will be useful, but
      21                 :             :    WITHOUT ANY WARRANTY; without even the implied warranty of
      22                 :             :    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
      23                 :             :    General Public License for more details.
      24                 :             : 
      25                 :             :    You should have received copies of the GNU General Public License and
      26                 :             :    the GNU Lesser General Public License along with this program.  If
      27                 :             :    not, see <http://www.gnu.org/licenses/>.  */
      28                 :             : 
      29                 :             : static bool
      30                 :           0 : x86_set_initial_registers_sample (const Dwarf_Word *regs, uint32_t n_regs,
      31                 :             :                                   uint64_t regs_mask, uint32_t abi,
      32                 :             :                                   Dwarf_Word *dwarf_regs, int expected_regs)
      33                 :             : {
      34                 :             : #if (!defined __i386__ && !defined __x86_64__) || !defined(__linux__)
      35                 :             :   return false;
      36                 :             : #else /* __i386__ || __x86_64__ */
      37                 :             :   /* The following facts are needed to translate x86 registers correctly:
      38                 :             :      - perf register order seen in linux arch/x86/include/uapi/asm/perf_regs.h
      39                 :             :        The registers array is built in the same order as the enum!
      40                 :             :        (See the code in tools/perf/util/intel-pt.c intel_pt_add_gp_regs().)
      41                 :             :      - EBL PERF_FRAME_REGS_MASK specifies all registers except segment and
      42                 :             :        flags.  However, regs_mask might be a different set of registers.
      43                 :             :        Again, regs_mask bits are in asm/perf_regs.h enum order.
      44                 :             :      - dwarf register order seen in elfutils backends/{x86_64,i386}_initreg.c
      45                 :             :        (matching pt_regs struct in linux arch/x86/include/asm/ptrace.h)
      46                 :             :        and it's a fairly different register order!
      47                 :             : 
      48                 :             :      For comparison, you can study codereview.qt-project.org/gitweb?p=qt-creator/perfparser.git;a=blob;f=app/perfregisterinfo.cpp;hb=HEAD
      49                 :             :      and follow the code which uses those tables of magic numbers.
      50                 :             :      But it's better to follow original sources of truth for this.  */
      51                 :             : 
      52                 :           0 :   bool is_abi32 = (abi == PERF_SAMPLE_REGS_ABI_32);
      53                 :             : 
      54                 :             :   /* Locations of dwarf_regs in the perf_event_x86_regs enum order,
      55                 :             :      not the regs[i] array (which will include a subset of the regs): */
      56                 :           0 :   static const int regs_i386[] = {0, 2, 3, 1, 7/*sp*/, 6, 4, 5, 8/*ip*/};
      57                 :           0 :   static const int regs_x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7/*sp*/,
      58                 :             :                                     16/*r8 after flags+segment*/, 17, 18, 19, 20, 21, 22, 23,
      59                 :             :                                     8/*ip*/};
      60         [ #  # ]:           0 :   const int *dwarf_to_perf = is_abi32 ? regs_i386 : regs_x86_64;
      61                 :             : 
      62                 :             :   /* Locations of perf_regs in the regs[] array, according to regs_mask: */
      63                 :           0 :   int perf_to_regs[PERF_REG_X86_64_MAX];
      64                 :           0 :   uint64_t expected_mask = is_abi32 ? PERF_FRAME_REGISTERS_I386 : PERF_FRAME_REGISTERS_X86_64;
      65                 :           0 :   int j, k; uint64_t bit;
      66                 :             :   /* TODO: Is it worth caching this perf_to_regs computation as long
      67                 :             :      as regs_mask is kept the same across repeated calls? */
      68         [ #  # ]:           0 :   for (j = 0, k = 0, bit = 1; k < PERF_REG_X86_64_MAX; k++, bit <<= 1)
      69                 :             :     {
      70   [ #  #  #  # ]:           0 :       if ((bit & expected_mask) && (bit & regs_mask)) {
      71         [ #  # ]:           0 :         if (n_regs <= (uint32_t)j)
      72                 :             :           return false; /* regs_mask count doesn't match n_regs */
      73                 :           0 :         perf_to_regs[k] = j;
      74                 :           0 :         j++;
      75                 :             :       } else {
      76                 :           0 :         perf_to_regs[k] = -1;
      77                 :             :       }
      78                 :             :     }
      79                 :             : 
      80         [ #  # ]:           0 :   for (int i = 0; i < expected_regs; i++)
      81                 :             :     {
      82                 :           0 :       k = dwarf_to_perf[i];
      83                 :           0 :       j = perf_to_regs[k];
      84         [ #  # ]:           0 :       if (j < 0) continue;
      85         [ #  # ]:           0 :       if (n_regs <= (uint32_t)j) continue;
      86                 :           0 :       dwarf_regs[i] = regs[j];
      87                 :             :     }
      88                 :             :   return true;
      89                 :             : #endif /* __i386__ || __x86_64__ */
      90                 :             : }