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1 : : /* x86 stack sample register handling helper common to x86-64 and i386.
2 : : Copyright (C) 2025-2026 Red Hat, Inc.
3 : : This file is part of elfutils.
4 : :
5 : : This file is free software; you can redistribute it and/or modify
6 : : it under the terms of either
7 : :
8 : : * the GNU Lesser General Public License as published by the Free
9 : : Software Foundation; either version 3 of the License, or (at
10 : : your option) any later version
11 : :
12 : : or
13 : :
14 : : * the GNU General Public License as published by the Free
15 : : Software Foundation; either version 2 of the License, or (at
16 : : your option) any later version
17 : :
18 : : or both in parallel, as here.
19 : :
20 : : elfutils is distributed in the hope that it will be useful, but
21 : : WITHOUT ANY WARRANTY; without even the implied warranty of
22 : : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 : : General Public License for more details.
24 : :
25 : : You should have received copies of the GNU General Public License and
26 : : the GNU Lesser General Public License along with this program. If
27 : : not, see <http://www.gnu.org/licenses/>. */
28 : :
29 : : #include "system.h"
30 : :
31 : : static inline bool
32 : 0 : x86_sample_perf_regs_mapping (Ebl *ebl,
33 : : uint64_t perf_regs_mask, uint32_t abi,
34 : : const int **regs_mapping,
35 : : size_t *n_regs_mapping)
36 : : {
37 [ # # # # ]: 0 : if (perf_regs_mask != 0 && ebl->cached_perf_regs_mask == perf_regs_mask)
38 : : {
39 : 0 : *regs_mapping = ebl->cached_regs_mapping;
40 : 0 : *n_regs_mapping = ebl->cached_n_regs_mapping;
41 : 0 : return true;
42 : : }
43 : :
44 : : /* The following facts are needed to translate x86 registers correctly:
45 : : - perf register order seen in linux arch/x86/include/uapi/asm/perf_regs.h
46 : : The registers array is built in the same order as the enum!
47 : : (See the code in tools/perf/util/intel-pt.c intel_pt_add_gp_regs().)
48 : : - EBL PERF_FRAME_REGS_MASK specifies all registers except segment and
49 : : flags. However, regs_mask might be a different set of registers.
50 : : Again, regs_mask bits are in asm/perf_regs.h enum order.
51 : : - dwarf register order seen in elfutils backends/{x86_64,i386}_initreg.c
52 : : (matching pt_regs struct in linux arch/x86/include/asm/ptrace.h)
53 : : and it's a fairly different register order!
54 : :
55 : : For comparison, you can study codereview.qt-project.org/gitweb?p=qt-creator/perfparser.git;a=blob;f=app/perfregisterinfo.cpp;hb=HEAD
56 : : and follow the code which uses those tables of magic numbers.
57 : : But it's better to follow original sources of truth for this. */
58 : :
59 : 0 : bool is_abi32 = (abi == PERF_SAMPLE_REGS_ABI_32);
60 : :
61 : : /* Locations of dwarf_regs in the perf_event_x86_regs enum order,
62 : : not the regs[] array (which will include a subset of the regs): */
63 : 0 : static const int regs_i386[] = {0, 2, 3, 1, 7/*sp*/, 6, 4, 5, 8/*ip*/};
64 : 0 : static const int regs_x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7/*sp*/,
65 : : 16/*r8 after flags+segment*/, 17, 18, 19, 20, 21, 22, 23,
66 : : 8/*ip*/};
67 [ # # ]: 0 : const int *dwarf_to_perf = is_abi32 ? regs_i386 : regs_x86_64;
68 : : /* regs_i386 and regs_x86_64 have different lengths; the mapping loop
69 : : below must not index dwarf_to_perf beyond the selected table. */
70 : 0 : size_t dwarf_to_perf_len = is_abi32 ?
71 : : sizeof (regs_i386) / sizeof (regs_i386[0]) :
72 : : sizeof (regs_x86_64) / sizeof (regs_x86_64[0]);
73 : :
74 : : /* Count bits and allocate regs_mapping: */
75 : 0 : int j, k, count; uint64_t bit;
76 : 0 : for (k = 0, count = 0, bit = 1;
77 [ # # ]: 0 : k < PERF_REG_X86_64_MAX; k++, bit <<= 1)
78 : : {
79 [ # # ]: 0 : if ((bit & perf_regs_mask)) {
80 : 0 : count++;
81 : : }
82 : : }
83 : 0 : ebl->cached_perf_regs_mask = perf_regs_mask;
84 : 0 : ebl->cached_regs_mapping = (int *)calloc (count, sizeof(int));
85 [ # # # # ]: 0 : if (count != 0 && ebl->cached_regs_mapping == NULL)
86 : : return false;
87 : 0 : ebl->cached_n_regs_mapping = count;
88 : :
89 : : /* Locations of perf_regs in the regs[] array, according to
90 : : perf_regs_mask. Initialize the whole array (not just up to the
91 : : highest set bit): the loop below indexes perf_to_regs[] by
92 : : dwarf_to_perf[i], which can be larger than the highest set bit in
93 : : perf_regs_mask. Leaving the tail uninitialized would read stack
94 : : garbage and could turn into an out-of-bounds write into the
95 : : cached_regs_mapping[] heap buffer. */
96 : 0 : int perf_to_regs[PERF_REG_X86_64_MAX];
97 : 0 : uint64_t expected_mask = is_abi32 ?
98 [ # # ]: 0 : PERF_FRAME_REGISTERS_I386 : PERF_FRAME_REGISTERS_X86_64;
99 [ # # ]: 0 : for (j = 0, k = 0, bit = 1; k < PERF_REG_X86_64_MAX; k++, bit <<= 1)
100 : : {
101 [ # # # # ]: 0 : if ((bit & expected_mask) && (bit & perf_regs_mask))
102 : : {
103 : 0 : perf_to_regs[k] = j;
104 : 0 : j++;
105 : : }
106 : : else
107 : : {
108 : 0 : perf_to_regs[k] = -1;
109 : : }
110 : : }
111 [ # # ]: 0 : if (j > (int)ebl->cached_n_regs_mapping)
112 : : return false;
113 : :
114 : : /* Locations of perf_regs in the dwarf_regs array, according to
115 : : perf_regs_mask and perf_to_regs[]. Bound by both frame_nregs and
116 : : the selected table length: when abi does not match the backend
117 : : either one can be the smaller (an x86_64 ebl with an ABI_32 sample
118 : : has frame_nregs 17 > 9, an i386 ebl with a 64-bit sample has
119 : : frame_nregs 9 < 17), so take the minimum once, up front. */
120 : 0 : size_t max_reg = MIN (ebl->frame_nregs, dwarf_to_perf_len);
121 [ # # ]: 0 : for (size_t i = 0; i < max_reg; i++)
122 : : {
123 : 0 : k = dwarf_to_perf[i];
124 : 0 : j = perf_to_regs[k];
125 [ # # # # ]: 0 : if (j < 0 || j >= (int)ebl->cached_n_regs_mapping) continue;
126 : 0 : ebl->cached_regs_mapping[j] = i;
127 : : }
128 : :
129 : 0 : *regs_mapping = ebl->cached_regs_mapping;
130 : 0 : *n_regs_mapping = ebl->cached_n_regs_mapping;
131 : 0 : return true;
132 : : }
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