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1 : : /* x86 stack sample register handling helper common to x86-64 and i386.
2 : : Copyright (C) 2025-2026 Red Hat, Inc.
3 : : This file is part of elfutils.
4 : :
5 : : This file is free software; you can redistribute it and/or modify
6 : : it under the terms of either
7 : :
8 : : * the GNU Lesser General Public License as published by the Free
9 : : Software Foundation; either version 3 of the License, or (at
10 : : your option) any later version
11 : :
12 : : or
13 : :
14 : : * the GNU General Public License as published by the Free
15 : : Software Foundation; either version 2 of the License, or (at
16 : : your option) any later version
17 : :
18 : : or both in parallel, as here.
19 : :
20 : : elfutils is distributed in the hope that it will be useful, but
21 : : WITHOUT ANY WARRANTY; without even the implied warranty of
22 : : MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 : : General Public License for more details.
24 : :
25 : : You should have received copies of the GNU General Public License and
26 : : the GNU Lesser General Public License along with this program. If
27 : : not, see <http://www.gnu.org/licenses/>. */
28 : :
29 : : static inline bool
30 : 0 : x86_sample_perf_regs_mapping (Ebl *ebl,
31 : : uint64_t perf_regs_mask, uint32_t abi,
32 : : const int **regs_mapping,
33 : : size_t *n_regs_mapping)
34 : : {
35 [ # # # # ]: 0 : if (perf_regs_mask != 0 && ebl->cached_perf_regs_mask == perf_regs_mask)
36 : : {
37 : 0 : *regs_mapping = ebl->cached_regs_mapping;
38 : 0 : *n_regs_mapping = ebl->cached_n_regs_mapping;
39 : 0 : return true;
40 : : }
41 : :
42 : : /* The following facts are needed to translate x86 registers correctly:
43 : : - perf register order seen in linux arch/x86/include/uapi/asm/perf_regs.h
44 : : The registers array is built in the same order as the enum!
45 : : (See the code in tools/perf/util/intel-pt.c intel_pt_add_gp_regs().)
46 : : - EBL PERF_FRAME_REGS_MASK specifies all registers except segment and
47 : : flags. However, regs_mask might be a different set of registers.
48 : : Again, regs_mask bits are in asm/perf_regs.h enum order.
49 : : - dwarf register order seen in elfutils backends/{x86_64,i386}_initreg.c
50 : : (matching pt_regs struct in linux arch/x86/include/asm/ptrace.h)
51 : : and it's a fairly different register order!
52 : :
53 : : For comparison, you can study codereview.qt-project.org/gitweb?p=qt-creator/perfparser.git;a=blob;f=app/perfregisterinfo.cpp;hb=HEAD
54 : : and follow the code which uses those tables of magic numbers.
55 : : But it's better to follow original sources of truth for this. */
56 : :
57 : 0 : bool is_abi32 = (abi == PERF_SAMPLE_REGS_ABI_32);
58 : :
59 : : /* Locations of dwarf_regs in the perf_event_x86_regs enum order,
60 : : not the regs[] array (which will include a subset of the regs): */
61 : 0 : static const int regs_i386[] = {0, 2, 3, 1, 7/*sp*/, 6, 4, 5, 8/*ip*/};
62 : 0 : static const int regs_x86_64[] = {0, 3, 2, 1, 4, 5, 6, 7/*sp*/,
63 : : 16/*r8 after flags+segment*/, 17, 18, 19, 20, 21, 22, 23,
64 : : 8/*ip*/};
65 [ # # ]: 0 : const int *dwarf_to_perf = is_abi32 ? regs_i386 : regs_x86_64;
66 : :
67 : : /* Count bits and allocate regs_mapping: */
68 : 0 : int j, k, kmax, count; uint64_t bit;
69 : 0 : for (k = 0, kmax = -1, count = 0, bit = 1;
70 [ # # ]: 0 : k < PERF_REG_X86_64_MAX; k++, bit <<= 1)
71 : : {
72 [ # # ]: 0 : if ((bit & perf_regs_mask)) {
73 : 0 : count++;
74 : 0 : kmax = k;
75 : : }
76 : : }
77 : 0 : ebl->cached_perf_regs_mask = perf_regs_mask;
78 : 0 : ebl->cached_regs_mapping = (int *)calloc (count, sizeof(int));
79 : 0 : ebl->cached_n_regs_mapping = count;
80 : :
81 : : /* Locations of perf_regs in the regs[] array, according to
82 : : perf_regs_mask: */
83 : 0 : int perf_to_regs[PERF_REG_X86_64_MAX];
84 : 0 : uint64_t expected_mask = is_abi32 ?
85 [ # # ]: 0 : PERF_FRAME_REGISTERS_I386 : PERF_FRAME_REGISTERS_X86_64;
86 [ # # ]: 0 : for (j = 0, k = 0, bit = 1; k <= kmax; k++, bit <<= 1)
87 : : {
88 [ # # # # ]: 0 : if ((bit & expected_mask) && (bit & perf_regs_mask))
89 : : {
90 : 0 : perf_to_regs[k] = j;
91 : 0 : j++;
92 : : }
93 : : else
94 : : {
95 : 0 : perf_to_regs[k] = -1;
96 : : }
97 : : }
98 [ # # ]: 0 : if (j > (int)ebl->cached_n_regs_mapping)
99 : : return false;
100 : :
101 : : /* Locations of perf_regs in the dwarf_regs array, according to
102 : : perf_regs_mask and perf_to_regs[]: */
103 [ # # ]: 0 : for (size_t i = 0; i < ebl->frame_nregs; i++)
104 : : {
105 : 0 : k = dwarf_to_perf[i];
106 : 0 : j = perf_to_regs[k];
107 [ # # ]: 0 : if (j < 0) continue;
108 : 0 : ebl->cached_regs_mapping[j] = i;
109 : : }
110 : :
111 : 0 : *regs_mapping = ebl->cached_regs_mapping;
112 : 0 : *n_regs_mapping = ebl->cached_n_regs_mapping;
113 : 0 : return true;
114 : : }
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