SH Options (Using the GNU Compiler Collection (GCC))

#### 3.20.46 SH Options ¶

These ‘`-m`’ options are defined for the SH implementations:

`-m1` ¶

  Generate code for the SH1.

`-m2` ¶

  Generate code for the SH2.

`-m2e` ¶

  Generate code for the SH2e.

`-m2a-nofpu` ¶

  Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way that the floating-point unit is not used.

`-m2a-single-only` ¶

  Generate code for the SH2a-FPU, in such a way that no double-precision floating-point operations are used.

`-m2a-single` ¶

  Generate code for the SH2a-FPU assuming the floating-point unit is in single-precision mode by default.

`-m2a` ¶

  Generate code for the SH2a-FPU assuming the floating-point unit is in double-precision mode by default.

`-m3` ¶

  Generate code for the SH3.

`-m3e` ¶

  Generate code for the SH3e.

`-m4-nofpu` ¶

  Generate code for the SH4 without a floating-point unit.

`-m4-single-only` ¶

  Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic.

`-m4-single` ¶

  Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default.

`-m4` ¶

  Generate code for the SH4.

`-m4-100` ¶

  Generate code for SH4-100.

`-m4-100-nofpu` ¶

  Generate code for SH4-100 in such a way that the floating-point unit is not used.

`-m4-100-single` ¶

  Generate code for SH4-100 assuming the floating-point unit is in single-precision mode by default.

`-m4-100-single-only` ¶

  Generate code for SH4-100 in such a way that no double-precision floating-point operations are used.

`-m4-200` ¶

  Generate code for SH4-200.

`-m4-200-nofpu` ¶

  Generate code for SH4-200 without in such a way that the floating-point unit is not used.

`-m4-200-single` ¶

  Generate code for SH4-200 assuming the floating-point unit is in single-precision mode by default.

`-m4-200-single-only` ¶

  Generate code for SH4-200 in such a way that no double-precision floating-point operations are used.

`-m4-300` ¶

  Generate code for SH4-300.

`-m4-300-nofpu` ¶

  Generate code for SH4-300 without in such a way that the floating-point unit is not used.

`-m4-300-single` ¶

  Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.

`-m4-300-single-only` ¶

  Generate code for SH4-300 in such a way that no double-precision floating-point operations are used.

`-m4-340` ¶

  Generate code for SH4-340 (no MMU, no FPU).

`-m4-400` ¶

  Generate code for SH4-400 (no MMU, no FPU).

`-m4-500` ¶

  Generate code for SH4-500 (no FPU). Passes `-isa=sh4-nofpu` to the assembler.

`-m4a-nofpu` ¶

  Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used.

`-m4a-single-only` ¶

  Generate code for the SH4a, in such a way that no double-precision floating-point operations are used.

`-m4a-single` ¶

  Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default.

`-m4a` ¶

  Generate code for the SH4a.

`-m4al` ¶

  Same as `-m4a-nofpu`, except that it implicitly passes `-dsp` to the assembler. GCC doesn’t generate any DSP instructions at the moment.

`-mb` ¶

  Compile code for the processor in big-endian mode.

`-ml` ¶

  Compile code for the processor in little-endian mode.

`-mdalign` ¶

  Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library do not work unless you recompile it first with `-mdalign`.

`-mrelax` ¶

  Shorten some address references at link time, when possible; uses the linker option `-relax`.

`-mbigtable` ¶

  Use 32-bit offsets in `switch` tables. The default is to use 16-bit offsets.

`-mbitops` ¶

  Enable the use of bit manipulation instructions on SH2A.

`-mfmovd` ¶

  Enable the use of the instruction `fmovd`. Check `-mdalign` for alignment constraints.

`-mrenesas` ¶
`-mno-renesas`

  Comply with the calling conventions defined by Renesas. The default for all targets of the SH toolchain is `-mno-renesas`, which uses the calling conventions defined for GCC before the Renesas conventions were available.

`-mnomacsave` ¶

  Mark the `MAC` register as call-clobbered, even if `-mrenesas` is given.

`-mieee` ¶
`-mno-ieee`

  Control the IEEE compliance of floating-point comparisons, which affects the handling of cases where the result of a comparison is unordered. By default `-mieee` is implicitly enabled. If `-ffinite-math-only` is enabled `-mno-ieee` is implicitly set, which results in faster floating-point greater-equal and less-equal comparisons. The implicit settings can be overridden by specifying either `-mieee` or `-mno-ieee`.

`-minline-ic_invalidate` ¶
`-mno-inline-ic_invalidate`

  Inline code to invalidate instruction cache entries after setting up nested function trampolines. This option has no effect if `-musermode` is in effect and the selected code generation option (e.g. `-m4`) does not allow the use of the `icbi` instruction. If the selected code generation option does not allow the use of the `icbi` instruction, and `-musermode` is not in effect, the inlined code manipulates the instruction cache address array directly with an associative write. This not only requires privileged mode at run time, but it also fails if the cache line had been mapped via the TLB and has become unmapped.

`-misize` ¶

  Dump instruction size and location in the assembly code.

`-matomic-model=model` ¶

  Sets the model of atomic operations and additional parameters as a comma-separated list. For details on the atomic built-in functions see Built-in Functions for Memory Model Aware Atomic Operations. The following models and parameters are supported:

  ‘`none`’

    Disable compiler generated atomic sequences and emit library calls for atomic operations. This is the default if the target is not `sh*-*-linux*`.

  ‘`soft-gusa`’

    Generate GNU/Linux-compatible gUSA software atomic sequences for the atomic built-in functions. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for SH3* and SH4* single-core systems. This option is enabled by default when the target is `sh*-*-linux*` and SH3* or SH4*. When the target is SH4A, this option also partially utilizes the hardware atomic instructions `movli.l` and `movco.l` to create more efficient code, unless ‘`strict`’ is specified.

  ‘`soft-tcb`’

    Generate software atomic sequences that use a variable in the thread control block. This is a variation of the gUSA sequences which can also be used on SH1* and SH2* targets. The generated atomic sequences require additional support from the interrupt/exception handling code of the system and are only suitable for single-core systems. When using this model, the ‘`gbr-offset=`’ parameter has to be specified as well.

  ‘`soft-imask`’

    Generate software atomic sequences that temporarily disable interrupts by setting `SR.IMASK = 1111`. This model works only when the program runs in privileged mode and is only suitable for single-core systems. Additional support from the interrupt/exception handling code of the system is not required. This model is enabled by default when the target is `sh*-*-linux*` and SH1* or SH2*.

  ‘`hard-llcs`’

    Generate hardware atomic sequences using the `movli.l` and `movco.l` instructions only. This is only available on SH4A and is suitable for multi-core systems. Since the hardware instructions support only 32-bit atomic variables, access to 8- or 16-bit variables is emulated with 32-bit accesses. Code compiled with this option is also compatible with other software atomic model interrupt/exception handling systems if executed on an SH4A system. Additional support from the interrupt/exception handling code of the system is not required for this model.

  ‘`gbr-offset=`’

    This parameter specifies the offset in bytes of the variable in the thread control block structure that should be used by the generated atomic sequences when the ‘`soft-tcb`’ model has been selected. For other models this parameter is ignored. The specified value must be an integer multiple of four and in the range 0-1020.

  ‘`strict`’

    This parameter prevents mixed usage of multiple atomic models, even if they are compatible, and makes the compiler generate atomic sequences of the specified model only.

`-mtas` ¶

  Generate the `tas.b` opcode for `__atomic_test_and_set`. Notice that depending on the particular hardware and software configuration this can degrade overall performance due to the operand cache line flushes that are implied by the `tas.b` instruction. On multi-core SH4A processors the `tas.b` instruction must be used with caution since it can result in data corruption for certain cache configurations.

`-mprefergot` ¶

  When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table.

`-musermode` ¶
`-mno-usermode`

  Don’t allow (allow) the compiler to generate privileged mode code. Specifying `-musermode` also implies `-mno-inline-ic_invalidate` if the inlined code would not work in user mode. `-musermode` is the default when the target is `sh*-*-linux*`. If the target is SH1* or SH2* `-musermode` has no effect, since there is no user mode.

`-multcost=number` ¶

  Set the cost to assume for a multiply instruction.

`-mdiv=strategy` ¶

  Set the division strategy to be used for integer division operations. strategy can be one of:

  ‘`call-div1`’

    Calls a library function that uses the single-step division instruction `div1` to perform the operation. Division by zero calculates an unspecified result and does not trap. This is the default except for SH4, SH2A and SHcompact.

  ‘`call-fp`’

    Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is the default for SHcompact with FPU. Specifying this for targets that do not have a double-precision FPU defaults to `call-div1`.

  ‘`call-table`’

    Calls a library function that uses a lookup table for small divisors and the `div1` instruction with case distinction for larger divisors. Division by zero calculates an unspecified result and does not trap. This is the default for SH4. Specifying this for targets that do not have dynamic shift instructions defaults to `call-div1`.

  When a division strategy has not been specified, the default strategy is selected based on the current target. For SH2A the default strategy is to use the `divs` and `divu` instructions instead of library function calls.

`-maccumulate-outgoing-args` ¶
`-mno-accumulate-outgoing-args`

  Reserve space once for outgoing arguments in the function prologue rather than around each call. This is generally beneficial for performance and size, and also needed for unwinding to avoid changing the stack frame around conditional code. `-maccumulate-outgoing-args` is enabled the default.

`-mdivsi3_libfunc=name` ¶

  Set the name of the library function used for 32-bit signed division to name. This only affects the name used in the ‘`call`’ division strategies, and the compiler still expects the same sets of input/output/clobbered registers as if this option were not present.

`-mfixed-range=register-range` ¶

  Generate code treating the given register range as fixed registers. A fixed register is one that the register allocator cannot use. This is useful when compiling kernel code. A register range is specified as two registers separated by a dash. Multiple register ranges can be specified separated by a comma.

`-mbranch-cost=num` ¶

  Assume num to be the cost for a branch instruction. Higher numbers make the compiler try to generate more branch-free code if possible. If not specified the value is selected depending on the processor type that is being compiled for.

`-mzdcbranch` ¶
`-mno-zdcbranch`

  Assume (do not assume) that zero displacement conditional branch instructions `bt` and `bf` are fast. If `-mzdcbranch` is specified, the compiler prefers zero displacement branch code sequences. This is enabled by default when generating code for SH4 and SH4A. It can be explicitly disabled by specifying `-mno-zdcbranch`.

`-mcbranch-force-delay-slot` ¶

  Force the usage of delay slots for conditional branches, which stuffs the delay slot with a `nop` if a suitable instruction cannot be found. By default this option is disabled. It can be enabled to work around hardware bugs as found in the original SH7055.

`-mfsca` ¶
`-mno-fsca`

  Allow or disallow the compiler to emit the `fsca` instruction for sine and cosine approximations. The option `-mfsca` must be used in combination with `-funsafe-math-optimizations`. It is enabled by default when generating code for SH4A. Using `-mno-fsca` disables sine and cosine approximations even if `-funsafe-math-optimizations` is in effect.

`-mfsrra` ¶
`-mno-fsrra`

  Allow or disallow the compiler to emit the `fsrra` instruction for reciprocal square root approximations. The option `-mfsrra` must be used in combination with `-funsafe-math-optimizations` and `-ffinite-math-only`. It is enabled by default when generating code for SH4A. Using `-mno-fsrra` disables reciprocal square root approximations even if `-funsafe-math-optimizations` and `-ffinite-math-only` are in effect.

`-mpretend-cmove` ¶
`-mno-pretend-cmove`

  Prefer or don’t prefer zero-displacement conditional branches for conditional move instruction patterns. This can result in faster code on the SH4 processor.

`-mfdpic` ¶
`-mno-fdpic`

  Generate code using the FDPIC ABI.